Publication:

Novel Design Strategy for High-Endurance (>10<SUP>10</SUP>) and Fast-Erase Oxide-Semiconductor Channel FeFET

Date

2024
Proceedings Paper
https://doi.org/10.1109/iedm50854.2024.10873449
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dc.contributor.authorChen, Zhuo
dc.contributor.authorKim, Hyun-Cheol
dc.contributor.authorZheng, Wei
dc.contributor.authorIzmailov, Roman
dc.contributor.authorTruijen, Brecht
dc.contributor.authorSubhechha, Subhali
dc.contributor.authorWalke, Amey
dc.contributor.authorVaisman Chasin, Adrian
dc.contributor.authorPopovici, Mihaela Ioana
dc.contributor.authorLi, Jie
dc.contributor.authorKruv, Anastasiia
dc.contributor.authorTang, Hongwei
dc.contributor.authorXi, Fengben
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorRosmeulen, Maarten
dc.contributor.authorRonchi, Nicolo
dc.contributor.authorAfanasiev, Valeri
dc.contributor.authorVan Houdt, Jan
dc.date.accessioned2026-05-18T09:13:38Z
dc.date.available2026-05-18T09:13:38Z
dc.date.createdwos2026-03-18
dc.date.issued2024
dc.description.abstractWe fabricate ALD Oxide-Semiconductor Channel (OSC) FeFETs on 300-mm wafers. New design strategies of OSC FeFETs by La:HZO/IGZO interfacial engineering and IGZO channel thickness/length scaling are implemented to achieve high endurance and faster erase. The impact of IGZO composition is investigated, revealing that In-poor IGZO improves both the Memory Window (MW) and Vt stability. High MW and state-of-art endurance (>1010 cycles) are demonstrated in novel dual-composition-channel FeFETs. With all layers grown by ALD, this advanced stack is promising for the 3D integration of OSC FeFETs in high-endurance, low-latency, and non-destructive-read memories.
dc.description.wosFundingTextThis work was supported by imec's Industrial Affiliation Program on Storage. The authors would like to thank Alexandru Pavel and Harinarayanan Puliyalil for the development of ALD OS deposition and etching.
dc.identifier.doi10.1109/iedm50854.2024.10873449
dc.identifier.issn2380-9248
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/59419
dc.language.isoeng
dc.provenance.editstepusergreet.vanhoof@imec.be
dc.publisherIEEE
dc.source.conferenceIEEE International Electron Devices Meeting (IEDM)
dc.source.conferencedate2024-12-07
dc.source.conferencelocationSan Francisco
dc.source.journal2024 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM
dc.source.numberofpages4
dc.title

Novel Design Strategy for High-Endurance (>1010) and Fast-Erase Oxide-Semiconductor Channel FeFET

dc.typeProceedings paper
dspace.entity.typePublication
imec.internal.crawledAt2026-04-07
imec.internal.sourcecrawler
imec.internal.wosCreatedAt2026-04-07
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