The critical role of 2D TMD interfacial layers for pFET performance

Abstract

We report on developments in 2D TMD interface engineering and the key role the interfacial layer (IL) plays on the performance of WSe2-based pFET devices. We show the first demonstration of ‘sacrificial’ TMD multilayers used as native TMD oxide IL for nucleation of a high-k ALD p-type compatible gate stack, resulting in low gate leakage of 10−3A/cm2. The WSe2 multilayers were grown with fab-compatible MOCVD on 300mm Si wafers and show no mobility degradation after sacrificial oxidation process. We also discuss metal seeding as an alternative method for forming an IL compatible with monolayer WSe2 channels and show that nearly degenerate doping is achieved after deposition of a thin Mo seed layer followed by optimized O2 annealing. As many literature reports of TMD pFET doping struggle with poor on/off ratio, we now report a novel co-seeding method, which enables controllable p-type doping, resulting in channel on-currents of more than one order of magnitude higher and on/off ratio's of ∼107, comparable to those of the pristine WSe2 channels.