Memristor-Assisted CDAC Background Calibration Scheme for SAR ADCs

Abstract

This paper proposes a Vref-compensated memristor-assisted CDAC background calibration scheme for Nyquist SAR ADCs. The proposed CDAC is implemented in a 12-bit 5 MS/s asynchronous SAR ADC featuring a Vcm-based switching scheme and designed using a standard 65 nm CMOS process. Capacitor mismatches are detected by introducing a redundant bit, which evaluates the sign of the mismatch error. This error is then calibrated through a feedback loop using voltage dividers with four integrated memristors. These programmable voltage dividers generate a compensating voltage that is added to or subtracted from the ADC reference voltage (Vref) based on the sign of the mismatch error. Consequently, the adjusted Vref compensates the CDAC output level to reduce non-linearity induced by capacitor mismatches. Simulation results validate the feasibility of optimizing non-linearity in moderate/high-resolution SAR ADCs (12-bit in this study) caused by capacitor mismatches, improving the signal-to-noise-and-distortion ratio (SNDR) from 41.85 dB to 65.98 dB with memristor-assisted analog circuits. The proposed SAR ADC occupies 0.0153 mm2 area according to the layout floorplan, making it a promising candidate for miniature/large-scale sensor interface application.