Publication:
Hybrid Channel monolithic-CFET with Si (110) pMOS and (100) nMOS
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| dc.contributor.author | Vandooren, Anne | |
| dc.contributor.author | Iacovo, Serena | |
| dc.contributor.author | Brissonneau, Vincent | |
| dc.contributor.author | Chiarella, Thomas | |
| dc.contributor.author | Cullen, C. | |
| dc.contributor.author | Casey, D. | |
| dc.contributor.author | Rengo, G. | |
| dc.contributor.author | Khazaka, R. | |
| dc.contributor.author | Eyben, Pierre | |
| dc.contributor.author | Channam, Venkat Sunil Kumar | |
| dc.contributor.author | Ganguly, Jishnu | |
| dc.contributor.author | Stiers, Karen | |
| dc.contributor.author | Sheng, Cassie | |
| dc.contributor.author | Toledo de Carvalho Cavalcante, Camila | |
| dc.contributor.author | Hosseini, Maryam | |
| dc.contributor.author | Batuk, Dmitry | |
| dc.contributor.author | Peng, A. | |
| dc.contributor.author | Zhou, X. | |
| dc.contributor.author | Sarkar, Ritam | |
| dc.contributor.author | Veloso, Anabela | |
| dc.date.accessioned | 2026-08-21T08:56:44Z | |
| dc.date.available | 2026-08-21T08:56:44Z | |
| dc.date.createdwos | 2026 | |
| dc.date.issued | 2025 | |
| dc.description.abstract | This work reports on the demonstration of a monolithic-CFET (mCFET) integrating different channels for nMOS and pMOS. We enhanced our conventional mCFET process with a (110) Si pMOS - (100) Si nMOS combination and a single film embedded middle dielectric insulator (eMDI) by means of layer transfer. Using this advanced substrate, these two new features can be integrated in any mCFET baseline with minimal modifications and reduced process complexity compared to a replacement MDI (rMDI) integration. Functional PMOS and NMOS devices featuring SiCN eMDI are reported. Key aspects related to the bonding dielectric interface and the C content in SiCN MDI are assessed. | |
| dc.description.wosFundingText | This research was funded by imec's Core Partner Program and EU projects. This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union's Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. | |
| dc.identifier.doi | 10.1109/iedm50572.2025.11353866 | |
| dc.identifier.isbn | 979-8-3315-6786-6 | |
| dc.identifier.issn | 2380-9248 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/60084 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | IEEE International Electron Devices Meeting (IEDM) | |
| dc.source.conferencedate | 2025-12-06 | |
| dc.source.conferencelocation | San Francisco | |
| dc.source.journal | 2025 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, IEDM | |
| dc.source.numberofpages | 4 | |
| dc.title | Hybrid Channel monolithic-CFET with Si (110) pMOS and (100) nMOS | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-07-14 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-07-14 | |
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