High-k scaling for reliability enhancement in 300-mm-integrated WS₂ FETs

Abstract

We study the effect of high-k dielectric scaling and annealing treatments on the reliability of 300-mmintegrated WS2 field-effect transistors (FETs). Under positive gate bias stress, devices featuring a 1.5nmAlOx/1+3nmHfO2 top-gate stack exhibit a significantly lower number of active defects compared to those with 1.5nmAlOx/8+3nmHfO2 or 1.5nmAlOx/3+3nmHfO2. The improvement is most pronounced in the low-stress bias regime, where the HfO2 defect band dominates device degradation. Transient TCAD simulations incorporating a non-radiative multiphonon model underscore two main factors behind this stability enhancement: fewer available defects in the thinner HfO2 layer, and a reduced defect density arising from either partial curing of plasma-induced defects or the preserved amorphous nature of the scaled HfO2. In addition to gate oxide scaling, we assess two annealing strategies: an H2S anneal performed prior to AlOx deposition, and a high-pressure (HP) H2 anneal applied post-fabrication. The HP H2 anneal yields the greatest stability enhancement, achieving an approximately twofold reduction in active defect density. These results provide insight into the development of reliable 2D FETs using industry-standard oxides.