Double-Row CFET: Design Technology Co-Optimization for Area Efficient A7 Technology Node

Abstract

Complementary FET (CFET) device architecture with stacked n-/p-FETs is an outstanding option, promising power, performance, area scalability in the post-FinFET device era. Among several options, the double-row (DR) CFET architecture leads to reduced process complexity in the middle-of-line (MOL), and gains in logic and SRAM area, by scaling to 3.5Tracks x CPP per 2 FETs. Projections show ~40% area and ~12% power scaling potential.