3.5T CFET Block-Level DTCO for Superior PPA in A7 Node by Split Power, hDR Cells, Optimized Pins and BEOL

Abstract

Complementary FETs (CFET), with the structure of stacked n-/p-FETs, hold promises for continuing shrinking device footprints after the nanosheet era. To realize CFET block-level designs with superior power-performance-area (PPA), several enhancements are introduced through design technology co-optimization (DTCO), such as a double-row split-power CFET structure, half-height double-row cells, as well as optimization in pins and back-end-of-line (BEOL). Results show that A7 3.5T CFET designs reach -46% area and iso-performance compared to N2 nanosheet designs.