Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height

Abstract

This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced Reff and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.