Exploring 2D TMD pFET Gate Stack Scalability Towards 1 Nm Electrical Thickness

Abstract

We report p-type compatible WOx/HfO2 gate stacks for WSe2-based 2D pFET devices. 2D pFET compatible gate stacks are challenging as typical 2D gate stack processes often result in unintentional n-type doping. In this work, we preserve the p-type attributes of the channel through ALD precursor optimization, while employing interfacial layers to maintain the channel integrity. Dual-gate devices are fabricated with channel length down to 50 nm and gate stacks achieving about 1.4 nm CET. We also present the first reported 2D pFET CV characteristics, including AC conductance analysis, showing successful CET scaling when thinning from 10 nm down to 4nmHfO2 physical thickness.