Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

Acharya, Lomash Chandra; Sharma, Arvind; Mishra, Neeraj; Singh, Khoirom Johnson; Dargupally, Mahipal; Shabarish, Nayakanti Sai; Mandal, Ajoy; Ramakrishnan, Venkatraman; Dasgupta, Sudeb; Bulusu, Anand

doi:10.1109/tcad.2022.3231173

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Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

Date

2023

Journal article

https://doi.org/10.1109/tcad.2022.3231173

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Author(s)

Acharya, Lomash Chandra

;

Sharma, Arvind

;

Mishra, Neeraj

;

Singh, Khoirom Johnson

;

Dargupally, Mahipal

;

Shabarish, Nayakanti Sai

;

Mandal, Ajoy

;

Ramakrishnan, Venkatraman

;

Dasgupta, Sudeb

;

Bulusu, Anand

Journal

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

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1086 since deposited on 2023-08-11

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Acq. date: 2026-08-18

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

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