Publication:
ARC: Application-Level Refinement and Cache Mapping for Performance Optimization on the Edge
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.department | #PLACEHOLDER_PARENT_METADATA_VALUE# | |
| cris.virtual.orcid | 0009-0005-5094-5701 | |
| cris.virtual.orcid | 0000-0002-0029-6548 | |
| cris.virtual.orcid | 0000-0002-3599-8515 | |
| cris.virtualsource.department | 0aba5169-585a-4a10-8bbd-7c7e93dac604 | |
| cris.virtualsource.department | f6f17b49-e3c3-4223-9429-3bcd739eacc2 | |
| cris.virtualsource.department | 7a992f6f-feea-493d-b4d8-c297450cff52 | |
| cris.virtualsource.orcid | 0aba5169-585a-4a10-8bbd-7c7e93dac604 | |
| cris.virtualsource.orcid | f6f17b49-e3c3-4223-9429-3bcd739eacc2 | |
| cris.virtualsource.orcid | 7a992f6f-feea-493d-b4d8-c297450cff52 | |
| dc.contributor.author | Katsaragakis, Manolis | |
| dc.contributor.author | Lamprakos, Christos | |
| dc.contributor.author | Kourzanov, Peter | |
| dc.contributor.author | Perumkunnil, Manu | |
| dc.contributor.author | Papadopoulos, Lazaros | |
| dc.contributor.author | Catthoor, Francky | |
| dc.contributor.author | Soudris, Dimitrios | |
| dc.date.accessioned | 2026-06-03T07:33:58Z | |
| dc.date.available | 2026-06-03T07:33:58Z | |
| dc.date.createdwos | 2026-02-10 | |
| dc.date.issued | 2025 | |
| dc.description.abstract | Recent advances in applications that are highly dependent on efficient cache utilization, in addition to the rapid growth of Edge computing systems deployed with emerging processors, generate a complex paradigm across the hardware and software continuum. In this work, we propose ARC, a novel systematic exploration methodology for application-level refinement and cache configuration mapping over emerging architectures for performance optimization. More specifically, our solution relies on workload partitioning and source code slicing mechanisms aiming to boost co-exploration of cache configuration parameters. Our proposed methodology is evaluated on a real-life IoT biomedical use case deployed over GEM5 RISC-V simulated system, showing that i) the co-impact of source code refinement and effective cache configuration leads to 61.1% execution time optimization, ii) the effective application organization and refinement leads to reduced hardware complexity. Last, we provide guidelines for application cache-friendly source code organization for performance optimization. | |
| dc.description.wosFundingText | This work has been partially funded by EU Horizon program CONVOLVE under grant agreement No 101070374 (https://convolve.eu). | |
| dc.identifier.doi | 10.1109/iscas56072.2025.11044229 | |
| dc.identifier.isbn | 979-8-3503-5684-7 | |
| dc.identifier.issn | 0271-4302 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/59512 | |
| dc.language.iso | eng | |
| dc.provenance.editstepuser | greet.vanhoof@imec.be | |
| dc.publisher | IEEE | |
| dc.source.conference | IEEE International Symposium on Circuits and Systems (ISCAS) | |
| dc.source.conferencedate | 2025-05-25 | |
| dc.source.conferencelocation | London | |
| dc.source.journal | 2025 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS | |
| dc.source.numberofpages | 5 | |
| dc.title | ARC: Application-Level Refinement and Cache Mapping for Performance Optimization on the Edge | |
| dc.type | Proceedings paper | |
| dspace.entity.type | Publication | |
| imec.internal.crawledAt | 2026-04-07 | |
| imec.internal.source | crawler | |
| imec.internal.wosCreatedAt | 2026-04-07 | |
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