Cu/SiCN Wafer-to-Wafer Hybrid Bonding Interface Reliability Down to 400 nm Pitch

Abstract

Increased development costs and device complexity have lead to a slow down of the traditional more Moore approach and promoted the rise of 3D technologies. By combining neatly chips originating from different tech-nology nodes through vertical interconnections, complex More than Moore Systems-on-Chip (SoC) designs, out of reach of the monolithic approach, are enabled. In this paradigm, vertical interconnection technologies are therefore key enablers, allowing higher densities with reduced latencies. In particular, wafer-to-wafer hybrid bonding technologies will be instrumental to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 106mm-2• In this article, the reliability of the Cu/SiCN bonding interface is evaluated in a 400 nm pitch wafer-to-wafer hybrid bonding technology. A lifetime assessment of the hybrid-bonding pad-to-pad interface is presented based on breakdown measurements performed at various temperatures. The evolution of the breakdown voltages and acceleration factors with the temperature support an intrinsic dielectric degradation, where copper migration along the bonding interface is unlikely to occur.