Towards a Low-Disorder pFET Gate Stack for Monolayer WSe₂ Channels

Abstract

Developing low-disorder deposited gate stacks for ultra-thin 2D channel materials remains a significant challenge, particularly for pFET devices. Conventional approaches, such as those derived from nFET/MoS2, often reduce mobility and degrade electrostatic control, while the use of transition metal oxide interlayers typically results in uncontrollable Vt shifts. In this work, we address these challenges by leveraging synthetic bilayer WSe2, which combines a low-defectivity monolayer channel material with optimized transfer and surface treatments. This approach achieves a low interface trap density (Dit) of (8–11)×10¹¹ /cm2•eV, subthreshold swings (SS) as low as 65 mV/decade, on/off ratio’s of over 107 and a median low-field mobility of 38 cm2/V•s, with a maximum of 85 cm2/V•s. These improvements lead to record high on-state currents of 108 μA/μm at a fixed, technology-relevant overdrive voltage of 1 V, and maximum current of 690 μA/μm. Furthermore, by optimizing WSe2 top-layer oxidation, we achieve controlled Vt shifts while maintaining device performance and enabling a top gate equivalent oxide thickness (EOT) of ~1.4nm – the smallest EOT reported for pFET devices with monolayer WSe2 channel.