S2RNN: Self-Supervised Reconfigurable Neural Network Hardware Accelerator for Machine Learning Applications

Abstract

Hardware implementation of neural networks (NNs) is challenging due to varying application requirements. This often necessitates creating specific field programmable gate arrays (FPGAs) configurations from scratch for each application. This article proposes a flexible, self-supervised reconfigurable method to fit several application requirements by providing only the maximum available computational nodes a priori. The proposed method dynamically reconfigures the required number of hidden layers and nodes based on the application. The goal is to automatically determine the optimal NN configuration through reconfigurability to achieve maximum accuracy. Optimality is demonstrated through minimum average power, average delay, and area overhead, as well as maximum throughput and accuracy. Experimental results show that the proposed approach significantly reduces the optimized architecture search cost (the number of online training iterations) and associated average power consumption for successive datasets/applications. The method’s effectiveness is shown both quantitatively and qualitatively, verified against the MNIST and CIFAR-10 classification problems. Our reconfigurable method demonstrates stable accuracy of 98.97% and 98.95% compared to state-of-the-art NNs with fixed configurations (98.85% and 73.0% for MNIST and 93.47% and 70.21% for CIFAR-10, respectively). Additionally, the proposed method shows a 20.9% reduction in average power dissipation compared to state-of-the-art methods. Implemented and tested using VHDL and Altera FPGA, the results indicate resource utilization comparable with the state-of-the-art method. This reconfigurability is especially advantageous for Internet of Things applications where power efficiency and adaptability to different tasks are critical.