Addressing Integration Challenges in Direct Backside Contact of CFET

Abstract

This work explores the integration challenges of direct backside contact (DBC) to the source and drain (SD) of the bottom PMOS in complementary field-effect transistors (CFET). We investigate various contact failures, including backside bottom contact opens and via contact opens. Through root cause analysis, we apply multiple integration approaches to mitigate these challenges. Our results demonstrate a significant improvement in PMOS DBC enhancing contact success rate.