Cost-Performance Co-Optimization for the Chiplet Era

Abstract

Chiplet technologies allow for greater flexibility in system design through a wide range of system configuration options spanning integration schemes (monolithic, 2.5D, 3D), heterogeneity in technology nodes, and partitioning of system resources. Each such configuration has implications on figures of merit such as cost, power and performance. Optimizing for one metric may come at the expense of the other two. During the initial architecture exploration and design planning stage, it is critical to conduct cost-performance co-optimization using models that cover the entire spectrum of configuration options to make an informed choice. This work presents an evaluation using a framework that models both cost and performance simultaneously for chiplet-based systems, enabling analysis of the impact of various system-wide architectural configurations. We analyze a representative scale-out system for high-performance computing workloads to investigate how factors like integration, partitioning, technology node choices, and system size affect power, performance, and cost. The results demonstrate that the optimal design choices vary depending on these factors, highlighting the insights early stage chiplet design space exploration can offer.