An Efficient, Dynamically Adjustable, Multipurpose Ultrasound Digitizer Array in 40 nm CMOS

Abstract

In this work, a test chip for a 32 channel ultrasound imaging digitizer for intra-cardiac echocardiography is presented. The focus of this design is on area- and power efficiency, as well as multi-purpose usage for various catheters. It contains 32 individual analog front-ends and 12 bit SAR ADCs operating at 40MS/s to enable off-chip digital beamforming. The analog front-end is programmable in power, bandwidth, gain and can be partially bypassed. The front-end bypass and slew-rate can be dynamically adjusted to save power during a receive period. On-chip supply regulation is included, which can be duty-cycled between receive periods to power down the system and save power. This leads to a power supply consumption between 4.5 and 14.1mW when always on, or between 0.37 and 1.15mW when duty-cycling at an 8% ratio. When operating at maximum power, an SFDR of 57.5dB and SNR of 56.1dB are achieved.The ADC performance can optionally be improved by clocking the array in 4 separate clock phases, resulting in lower peak currents, less power supply disturbance and an overall linearity improvement of 6dB. The 32 channel array occupies 1mm2 including decoupling capacitance, combining low area and low power operation.