Breaking Thermal Bottleneck in 3D HBM-on-GPU Integration via System-Technology Co-Optimization

Abstract

The integration of High Bandwidth Memory (HBM) stacks directly atop GPUs offers bandwidth and package density but introduces severe thermal constraints. This work presents a thermal analysis and co-optimization approach for 3D HBM-on-GPU architectures under realistic power and packaging conditions. Within a consistent simulation environment, we evaluate a suite of technology- and system-level mitigation strategies, including HBM base die removal, HBM DRAM die merging, GPU frequency scaling, and doublesided cooling. Results show that peak GPU temperature can be reduced from 141.7°C to 70.8°C, with potential for improved throughput density (performance per unit package area) over 2.5D integration. This study highlights the importance of cross-layer thermal co-design and demonstrates the viability of HBM-on-GPU 3D stacking.