Chiplet Interconnect Test and Repair

Abstract

This research work addresses various challenges in testing and repairing chiplet-based (2.5D and 3D) multi-die integrated circuits (ICs) as manufacturing shifts toward complex, ultra-dense circuits with large amounts of die-to-die interconnects by micro-bump or hybrid-bump connections and possibly through-silicon vias (TSVs). Conventional interconnect testing methods are limited to detecting hard defects, leading to ineffectiveness, and cover many unrealistic shorts, causing inefficiency. This article introduces E2I-TEST, a method which covers, for a given collection of interconnects, all hard and weak variants of only realistic short, open, and coupling defects. E2I-TEST also prevents aliasing, thus supporting fault diagnosis. While it is predicted that the number of interconnects will rise significantly in the near future, E2I-TEST provides a high-quality interconnect test for which the number of test patterns is constant and no longer dependent on the number of interconnects. To further enhance the yield and reliability of chiplet-based systems, we propose a standardized repair description language for interoperable repair logic of inter-die interconnects, allowing vendors to describe or specify repair structures for automatic verification across various repair logic. We also develop a streamlined, polynomial-time repair algorithm for UCIe designs, minimizing their impact on signal rerouting. Finally, we present micro-bump map optimizations to reduce catastrophic defects and lower the spare interconnect usage. This work provides a comprehensive testing and repair framework, enhancing defect resilience and yield in future ICs.