Browsing by Author "Katti, Guruprasad"

3-D technology assessment: path-finding the technology/design sweet-spot

3D stacked IC demonstration using a through silicon via first approach

3D stacked IC demonstrator using hybrid collective die-to-wafer bonding with copper through silicon vias (TSV)

3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding

3D technology roadmap and status

Capacitance measurements of 2-dimensional and 3-dimensional IC interconnect structures by quasi-static C-V technique

Capacitance reduction technique for through silicon via (TSV) in p-Si substrate

Characterization and modeling of through silicon via (TSV) and its impact on 3D circuits and systems

Design, verification and simulation of 3D circuit

Electrical modeling and characterization of through silicon via for three-dimensional ICs

Impact of thinning and through silicon via proximity on high-k / metal gate first CMOS performance

Technology assessment of through-silicon via by using C-V and C-t Measurements

Temperature dependent electrical characteristics of through-si-via (TSV) interconnections

Temperature-dependent modeling and characterization of Through Silicon Via (TSV) capacitance

Test structures for characterization of through silicon vias

Test structures for characterization of through-silicon vias

TSV characterization and modeling

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack – challenges and solutions